In a prior approach for powering down a circuit system, when the system goes into sleep/data retention mode, the main power supply VDD goes from 1.3V (in active mode) to near 0V, a retaining power supply VRET remains unchanged at, for example, 1.3V, a retain signal RET goes from 0V to VRET (1.3V) level, and some internal nodes of the system are raised to a reference voltage VBB level (for example 0.6V).
For circuits whose data needs to be retained when the system goes into sleep/data retention mode, the typical way of turning off the P Channel (PCH) device is shown below:    Vdrain=VBB (0V-->0.6V, for example)    Vgate=RET (0-->1.3V, for example)    Vsource=VDD (1.3V-->0V, for example)    Vbulk=VRET (1.3V, for example)
This is demonstrated in the wordline circuit shown in FIG. 1. This circuit has a P channel device 20 as a header. The circuit also includes P channel device 22, N channel device 24, and N channel device 26. When this circuit goes into sleep/data retention mode, source voltage Vsource goes from the active level power supply level VDD (for example 1.3V) to 0V; the drain voltage Vdrain goes to the reference voltage VBB (for example 0.6V); the gate voltage Vgate goes to the retain signal RET, which goes from 0V to retaining power supply VRET (1.3V, for example); and the back gate Vbulk goes to the retaining power supply VRET.
The problem with this prior art solution is that large voltage differences between the gate (1.3V) and the source (0V)/drain (0.6V) exist which results in large gate tunneling leakage, which dominates the P channel device leakage at room temperature since the sub-threshold leakage is suppressed by the deep back-gate bias. This leads to high standby power consumption.